标题:
具效能和功率考虑之动态电压规划技术与自动化流程设计之实现Dynamic Voltage Assignment Technique for Cell Based Design under Power and Performance Constraints
作者:
郑经华
关键字:
低功率, 多电源区域Low Power Design; Multi Voltage Domain
期刊名称:
《Open Journal of Circuits and Systems》, Vol.2 No.2, 2013-06-19
摘要:
降低电压可以有效减少功率消耗，但是严重影响电路效能。为了维持芯片在相同的效能下工作，又要节省消耗功率，我们使用多电压源的设计作法。使用多电压源的芯片设计方法就是在关键路径(Critical Path)上的组件使用高电压，而非关键路径(Non-Critical Path)上的组件则使用低电压源。这样子就可以使电路在具相同的效能之下，还可以有效的节省功率。将我们的设计应用在相同的电路，可以让使用者选用不同的效能与功率消耗的组合模式，我们采用双电源的方式设计芯片，对于双电压源上的组件分布，还有组件如何给定不同的电压，及低准位和高准位输出之间的转换，这些都是需要考虑的范围。所以如何实现出这种可规划电压的电路设计方法，还有将这些组件做群组，并做适当的摆放来减少面积增加的问题，与如何控制这些组件的电压，并将此双电源设计在MPEG VLD的芯片，成功的实现依效能与功率消耗区分为三段的调节模式：快速、正常与省电，芯片成功实证此方法除可降低功率外，并可有效用于功率管理，功率节省范围可达65%。Lowering on selected blocks helps to reduce power significantly. Unfortunately, lowering the voltage also increases the delay of the gates in the design. Multi-voltage design is an effective way to reduce power consump- tion. High voltage is applied to the critical function or path, while low voltage is applied to non-critical paths. If the designer wants to choose different performance levels in the same design, designer needs to know how to program the voltage of the cell. This method reduces power consumption and not only maintains the same circuit performance but also saves power. In the proposed methodology of this paper, supply voltage applied to logic gates is programmable, and logic gates can be specified to high or low voltage domains according to operating system requirements. In order not to violate the delay time, the logic gates on the critical path require higher voltage. Lower voltage on the logic gates can be assigned to partial non-critical paths simultaneously. In the proposed method, the power switches possess the feature of flexible programming. They can easily be controlled according to the user requirement after chip manufacture. The potential of this design is that voltage domain can be switched to either high or low based on different design con- straints, e.g. voltage drop and temperature increase. The characteristic of this mechanism is programmable re-design of voltage domain after chip fabrication. The chip function proof this novel methodology is fully successful used in power-performance tradeoff application.