同步TP RAM的低功耗设计方法
A Low Power Design Method for Synchronous TP RAM
DOI: 10.12677/OJCS.2017.62005, PDF, HTML, XML, 下载: 1,562  浏览: 3,059 
作者: 周新格：西安高新唐南中学，陕西 西安；周清军：西安培华学院中兴电信学院，陕西 西安
关键词: 同步TP RAM；SP RAM；格雷码；动态电压调整；电源分区策略；TP RAM； SP RAM； Gray Code； Dynamic Voltage Regulation； Power Partition Strategy
摘要: 针对SoC中同步TP RAM的功耗较大问题，提出一种设计方法。通过将SoC中的同步TP RAM替换成SP RAM，在SP RAM外围增加读写接口转换逻辑，使替换后的RAM实现原TP RAM的功能，保持对外接口不变。为了进一步降低功耗，对地址总线进行格雷编码，采用动态电压调整技术及合理的电源分区策略。将文中方法应用于一款多核SoC芯片，经TSMC 28 nm HPC工艺实现。仿真结果表明：优化后的RAM面积减少了24.76%，功耗降低了44.89%。
Abstract: As the power consumption of synchronous TP RAM in SoC is large, a new design method of opti-mization is proposed. In order to achieve the function of the original TP RAM and keep the exter-nal interface unchanged, TP RAM is replaced with SP RAM, and read-write interface logics of con-version are added around SP RAM. For less power, address bus is encoded through Gray code; dynamic voltage regulation and reasonable power partition strategy are used. The method discussed in this paper is used in the multi core SoC chip which has been implemented in TSMC 28nm HPC process. The simulation results indicate that the area of optimized RAMs is reduced by 24.76%, and the power saving is reduced by 44.89%.
文章引用：周新格, 周清军. 同步TP RAM的低功耗设计方法[J]. 电路与系统, 2017, 6(2): 40-46. https://doi.org/10.12677/OJCS.2017.62005

参考文献

[1] Chiu, P.F. (2012) Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM with Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. IEEE Journal of Solid-State Circuits, 47, 1483-1496.
https://doi.org/10.1109/JSSC.2012.2192661
[2] Aghamohammadi, M.R. and Abdolahinia, H. (2014) A New Approach for Optimal Sizing of Battery Energy Storage System for Primary Frequency Control of Islanded Microgrid. International Journal of Electrical Power and Energy Systems, 54, 325-333.
[3] 柏娜, 冯越, 尤肖虎, 等. 极低电源电压和极低功耗的亚阈值SRAM存储单元设计[J]. 东南大学学报: 自然科学版, 2013, 43(2): 268-273.
[4] 张丽, 庄奕琪, 赵巍胜, 等. 一种适用于自旋磁随机存储器的低压写入电路[J]. 西安电子科技大学学报: 自然科学版, 2014, 43(3): 131-136.
[5] Peng, S.Y., Huang, T.C., Lee, Y.H., et al. (2013) Instruc-tion-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor with 53% Power Savings. IEEE Journal of Solid-State Circuits, 48, 2649-2661.
https://doi.org/10.1109/JSSC.2013.2274885
[6] 李栋, 王小力, 杨斌, 等. SoC总线的低功耗分支编码方案[J]. 计算机应用, 2014, 34(12): 3633-3636.
[7] 刘钱, 何炎祥, 廖希密, 等. 面向总线的低功耗优化方法探究[J]. 计算机工程与应用, 2014, 50(12): 42-47.
[8] 尚军辉. 通用SOC系统的低功耗设计方法[J]. 中国集成电路, 2013, 22(9): 23-30.
[9] Sally, W.-F. (2012) Wireless SoCs Use Cortex-MO Core to Slash Power Consumption. Microwaves & RF, 51, 36.
[10] Mahdoum, A. (2012) Combined Heuristics for Synthesis of SOCs with Time and Power Constraints. Computers and Electrical Engineering, 38, 1687-1702.
[11] 刘军, 钱庆庆, 吴玺, 等. 三维IP核绑定前后总测试时间的优化方法[J]. 计算机工程与应用, 2016, 52(22): 44-48, 54.